Today's digital logic based electronic systems can have a logic complexity implemented in hardware comparable to the logic employed in software systems developed only a few years ago. Many such systems have achieved this complexity by relying on programmable logic devices (PLD) to perform data processing, manipulation, and control.
One consequence of implementing high complexity logic in hardware is that, as with complex software programs, it may be desirable to make logic changes subsequent to releasing finished designs into the market. Such changes may be dictated by the discovery of bugs in the logic design or by the necessity or desire to increase or change functionality of the systems after they have been deployed. PLDs that have the capability to be reprogrammed could be modified with such bug fixes, changes, enhanced functionality, or for many other reasons if a mechanism is available to deliver that new functionality to the PLD.
One category of PLD having this reprogramming capacity is the field programmable gate array (FPGA). FPGAs typically include an array of logic function generators or configurable logic elements, input/output ports, and a matrix of interconnect lines. The configurable logic elements are generally embedded in and connectable to the matrix of interconnect lines The input/output ports are usually located at the perimeter of the FPGA and are connectable both to interconnect lines and to external pins. FPGAs are configured by programming memory elements, such as static RAM cells, anti-fuses, EPROM cells, and EEPROM cells, which control configuration of the device. Depending on the programming of the memory elements, the configurable logic elements will perform different logic functions and be connected to each other and to the input/output ports in a variety of ways. In general, FPGAs also include programmable memory cells to configure other features on the IC. For instance, the routing of clock signals and the use of multiple clock nets on an FPGA is often programmably selectable by the user.
Static-RAM-cell based FPGAs are configured each time the system in which they reside is powered on. Such FPGAs can also be reconfigured by sending appropriately designed reconfiguration signals to the FPGA. In general, these static-RAM-cell based FPGAs rely on external memory devices comprising nonvolatile memory cells to hold the configuration data for the FPGA. These external nonvolatile memories supply that configuration data in response to signals generated by the FPGA or a controller that controls configuration of the FPGA.
Many systems incorporating reconfigurable FPGAs that rely on external nonvolatile memories to hold their configuration data have not been designed to allow changes in the configuration data stored in the nonvolatile memories. Thus, although the FPGAs have the inherent capacity to be reconfigured, once the FPGAs are designed into such systems the configuration data that determines the FPGA functionality is not easily changed. Because this configuration data typically resides in memories that are not in-system reprogrammable, a change in configuration data requires changing the nonvolatile memories residing in the system. Such systems are not amenable to remote updating/changing of configuration data.
It has been proposed that utilizing Internet Reconfigurable Logic (IRL) would be a viable technique to upgrade system hardware from a remote location. However, the hardware required for internet connectivity would most likely require complete system redesign and this would not be feasible or cost effective for many existing systems. Moreover, although many designers know that the capacity for remote updating can be designed into a system, these designers nevertheless elect not to provide such capability in the systems they are designing because of the inherent associated costs in hardware, software, and extra time to design and test such system functionality.
It is desirable then to provide a simple low cost method and apparatus for the remote updating of PLD configuration data for the large number of existing systems that were not designed with such remote updating capability. It is further desirable to provide a simple low cost method and apparatus for the remote updating of any PLD based system without the necessity of designing specialized hardware or communications protocols into the system containing the PLD(s).